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1 msps, 8-channel, software-selectable, true bipolar input, 12-bit plus sign adc ad7329 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2010 analog devices, inc. all rights reserved. features 12-bit plus sign sar adc true bipolar input ranges software-selectable input ranges 10 v, 5 v, 2.5 v, 0 v to +10 v 1 msps throughput rate 8 analog input channels with channel sequencer single-ended true differential and pseudo differential analog input capability high analog input impedance mux out and adc in pins allow separate access to mux and adc low power: 21 mw temperature indicator full power signal bandwidth: 20 mhz internal 2.5 v reference high speed serial interface i cmos process technology 24-lead tssop package power-down modes functional block diagram v in 0 v in 1 v in 2 v in 3 v in 4 v in 5 v in 6 v in 7 ad7329 agnd v ss v drive din cs sclk dout v cc ref in /ref out v dd adc in ?adc in + mux out +mux out ? t/h channel sequencer 13-bit successive approximation adc control logic and registers i/p mux 2.5v vref 05402-001 figure 1. general description the ad7329 1 is an 8-channel, 12-bit plus sign successive approximation adc designed on the i cmos? (industrial cmos) process. i cmos is a process combining high voltage cmos and low voltage cmos. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts could achieve. unlike analog ics using conventional cmos processes, i cmos components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size. the ad7329 can accept true bipolar analog input signals. the ad7329 has four software-selectable input ranges: 10 v, 5 v, 2.5 v, and 0 v to +10 v. each analog input channel can be independently programmed to one of the four input ranges. the analog input channels on the ad7329 can be programmed to be single-ended, true differential, or pseudo differential. the adc contains a 2.5 v internal reference. the ad7329 also allows for external reference operation. if a 3 v reference is applied to the ref in /ref out pin, the ad7329 can accept a true bipolar 12 v analog input. the adc has a high speed serial interface that can operate at throughput rates up to 1 msps. product highlights 1. the ad7329 can accept true bipolar analog input signals, 1 0 v, 5 v, 2 . 5 v, a n d 0 v t o + 1 0 v u n i p o l a r s i g n a l s . 2. the eight analog inputs can be configured as eight single- ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. 3. 1 msps serial interface. spi?-/qspi?-/dsp-/microwire?- compatible interface. 4. low power, 21 mw, at 1 msps. 5. the mux out and adc in pins allow for signal conditioning of the mux output prior to entering the adc. table 1. similar devices device number throughput rate number of channels ad7328 1000 ksps 8 ad7327 500 ksps 8 ad7324 1000 ksps 4 ad7323 500 ksps 4 ad7322 1000 ksps 2 ad7321 500 ksps 2 1 protected by u.s. patent no. 6,731,232.
ad7329 rev. a | page 2 of 40 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 7 ? absolute maximum ratings ............................................................ 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 11 ? terminology .................................................................................... 15 ? theory of operation ...................................................................... 17 ? circuit information .................................................................... 17 ? converter operation .................................................................. 17 ? output coding ............................................................................ 18 ? transfer functions...................................................................... 18 ? analog input structure .............................................................. 18 ? track-and-hold section ............................................................ 19 ? typical connecti on diagram ................................................... 20 ? analog input ............................................................................... 20 ? driver amplifier choice ............................................................ 23 ? registers ........................................................................................... 25 ? addressing registers .................................................................. 25 ? control register ......................................................................... 26 ? sequence register ....................................................................... 28 ? range registers ........................................................................... 28 ? sequencer operation ..................................................................... 29 ? reference ..................................................................................... 31 ? v drive ............................................................................................ 31 ? temperature indicator ............................................................... 31 ? modes of operation ....................................................................... 32 ? normal mode (pm1 = pm0 = 0) ............................................. 32 ? full shutdown mode (pm1 = pm0 = 1) ................................. 32 ? autoshutdown mode (pm1 = 1, pm0 = 0) ............................. 33 ? autostandby mode (pm1 = 0, pm0 =1) ................................. 33 ? power vs. throughput rate ....................................................... 34 ? serial interface ................................................................................ 35 ? microprocessor interfacing ........................................................... 36 ? ad7329 to adsp-21xx .............................................................. 36 ? ad7329 to adsp-bf53x ........................................................... 36 ? applications information .............................................................. 37 ? layout and grounding .............................................................. 37 ? power supply configuration .................................................... 37 ? outline dimensions ....................................................................... 38 ? ordering guide .......................................................................... 38 ? revision history 2/10rev. 0 to rev. a changes to dc accuracy parameter, test conditions/ comments, table 2 ....................................................................... 4 change to normal mode (operational) i cc and i drive parameter and to power dissipation normal mode parameter, table 2 ........................................................................ 6 changes to table 16 and table 17 ................................................ 36 added applications information section, figure 60, and table 18 ................................................................................ 37 changes to ordering guide .......................................................... 38 4/06revision 0: initial version
ad7329 rev. a | page 3 of 40 specifications v dd = 12 v to 16.5 v, v ss = ?12 v to ?16.5 v, v cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v, v ref = 2.5 v internal/external, f sclk = 20 mhz, f s = 1 msps, t a = t max to t min , unless otherwise noted. mux out + is connected directly to adc in + and mux out ? is connected directly to adc in ?, which is connected to gnd for single-ended mode. table 2. b version parameter 1 min typ max unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise ratio (snr) 76 77 db differential mode 72.5 74 db single-ended/pseudo differential mode signal-to-noise and distortion (sinad) 2 75 76.5 db differential mode; 2.5 v and 5 v ranges 76.5 db differential mode; 0 v to +10 v and 10 v ranges 72 73.5 db single-ended/pseudo differential mode; 2.5 v and 5 v ranges 73.5 db single-ended/pseudo differential mode; 0 v to +10 v and 10 v ranges total harmonic distortion (thd) 2 ?87 ?80 db differential mode; 2.5 v and 5 v ranges ?85 db differential mode; 0 v to +10 v and 10 v ranges ?82 ?77 db single-ended/pseudo differential mode; 2.5 v and 5 v ranges ?80 db single-ended/pseudo differential mode; 0 v to +10 v and 10 v ranges peak harmonic or spurious noise (sfdr) 2 ?88 ?80 db differential mode; 2.5 v and 5 v ranges ?86 db differential mode ; 0 v to +10 v and 10 v ranges ?84 ?78 db single-ended/pseudo differential mode; 2.5 v and 5 v ranges ?82 db single-ended/pseudo differential mode; 0 v to +10 v and 10 v ranges intermodulation distortion (imd) 2 fa = 50 khz, fb = 30 khz second-order terms ?88 db third-order terms ?90 db aperture delay 3 7 ns aperture jitter 3 50 ps common-mode rejection (cmrr) 2 ?79 db up to 100 khz ripple frequency; see figure 17 channel-to-channel isolation 2 ?75 db f in on unselected channels up to 100 khz; see figure 14 full power bandwidth 20 mhz at 3 db 1.5 mhz at 0.1 db
ad7329 rev. a | page 4 of 40 b version parameter 1 min typ max unit test conditions/comments dc accuracy 4 all dc accuracy specifications are typical for 0 v to 10 v mode single-ended/pseudo differential mode 1 lsb = fsr/4096, unless otherwise noted differential mode 1 lsb = fsr/8192, unless otherwise noted resolution 13 bits no missing codes 12-bit plus sign (13 bits) bits differential mode 11-bit plus sign (12 bits) bits single-ended/pseudo differential mode integral nonlinearity 2 1.1 lsb differential mode 1 lsb single-ended/pseudo differential mode ?0.7/+1.2 lsb single-ended/pseudo differential mode (lsb = fsr/8192) differential nonlinearity 2 ?0.9/+1.5 lsb differential mode; guaranteed no missing codes to 13 bits 0.9 lsb single-ended mode; guaranteed no missing codes to 12 bits ?0.7/+1 lsb single-ended/pseudo differential mode (lsb = fsr/8192) offset error 2 , 5 ?4/+9 lsb single-ended/pseudo differential mode ?7/+10 lsb differential mode offset error match 2 , 5 0.6 lsb single-ended/pseudo differential mode 0.5 lsb differential mode gain error 2 , 5 8.0 lsb single-ended/pseudo differential mode 14 lsb differential mode gain error match 2 , 5 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode positive full-scale error 2 , 6 4 lsb single-ended/pseudo differential mode 7 lsb differential mode positive full-scale error match 2 , 6 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode bipolar zero code error 2 , 6 8.5 lsb single-ended/pseudo differential mode 7.5 lsb differential mode bipolar zero code error match 2 , 6 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode negative full-scale error 2 , 6 4 lsb single-ended/pseudo differential mode 6 lsb differential mode negative full-scale error match 2 , 6 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode
ad7329 rev. a | page 5 of 40 b version parameter 1 min typ max unit test conditions/comments analog input input voltage ranges reference = 2.5 v; see table 6 (programmed via range register) 10 v v dd = 10 v min, v ss = ?10 v min, v cc = 2.7 v to 5.25 v 5 v v dd = 5 v min, v ss = ?5 v min, v cc = 2.7 v to 5.25 v 2.5 v v dd = 5 v min, v ss = ? 5 v min, v cc = 2.7 v to 5.25 v 0 to 10 v v dd = 10 v min, v ss = agnd min, v cc = 2.7 v to 5.25 v pseudo differential v in ? input range v dd = 16.5 v, v ss = ?16.5 v, v cc = 5 v; see figure 43 and figure 44 3.5 v reference = 2.5 v; range = 10 v 6 v reference = 2.5 v; range = 5 v 5 v reference = 2.5 v; range = 2.5 v +3/?5 v reference = 2.5 v; range = 0 v to +10 v dc leakage current 100 na v in = v dd or v ss 3 na per channel, v in = v dd or v ss input capacitance 3 16 pf when in track, all ranges, single ended adc in capacitance 3 7 pf when in track, 10 v range, single ended 10 pf when in track, 5 v range, single ended 14.5 pf when in track, 2.5 v range, single ended 10.5 pf when in track, 0 v to +10 v range, single ended 4.0 pf when in hold, all ranges, single ended mux out ? capacitance 3 7.5 pf all ranges, single ended mux out + capacitance 3 13 pf all ranges, single ended reference input/output input voltage range 2.5 3 v input dc leakage current 1 a input capacitance 10 pf reference output voltage 2.5 v reference output voltage error @ 25c 5 mv reference output voltage t min to t max 10 mv reference temperature coefficient 25 ppm/c 3 ppm/c reference output impedance 7 logic inputs input high voltage, v inh 2.4 v input low voltage, v inl 0.8 v v cc = 4.75 v to 5.25 v 0.4 v v cc = 2.7 to 3.6 v input current, i in 1 a v in = 0 v or v drive input capacitance, c in 3 10 pf logic outputs output high voltage, v oh v drive ? 0.2 v v i source = 200 a output low voltage, v ol 0.4 v i sink = 200 a floating-state leakage current 1 a floating-state output capacitance 3 5 pf output coding straight natural binary coding bit set to 1 in control register twos complement coding bit set to 0 in control register
ad7329 rev. a | page 6 of 40 b version parameter 1 min typ max unit test conditions/comments conversion rate conversion time 800 ns 16 sclk cycles with sclk = 20 mhz track-and-hold acquisition time 2 , 3 300 ns full-scale step input; see the terminology section throughput rate 1 msps v cc = 4.75 v to 5.25 v; see the serial interface section 770 ksps v cc < 4.75 v power requirements digital inputs = 0 v or v drive v dd 12 16.5 v see table 6 v ss ?12 ?16.5 v see table 6 v cc 2.7 5.25 v see table 6 ; typical specifications for v cc < 4.75 v v drive 2.7 5.25 v normal mode (static) 0.9 ma v dd = 16.5, v ss = ?16.5 v, v cc = v drive = 5.25 v normal mode (operational) f s = 1 msps i dd 360 a v dd = 16.5 v i ss 410 a v ss = ?16.5 v i cc and i drive 3.4 ma v cc = v drive = 5.25 v autostandby mode (dynamic) f s = 250 ksps i dd 200 a v dd = 16.5 v i ss 210 a v ss = ?16.5 v i cc and i drive 1.3 ma v cc = v drive = 5.25 v autoshutdown mode (static) sclk on or off i dd 1 a v dd = 16.5 v i ss 1 a v ss = ?16.5 v i cc and i drive 1 a v cc = v drive = 5.25 v full shutdown mode sclk on or off i dd 1 a v dd = 16.5 v i ss 1 a v ss = ?16.5 v i cc and i drive 1 a v cc = v drive = 5.25 v power dissipation normal mode (operational) 31 mw v dd = 16.5 v, v ss = ?16.5 v, v cc = 5.25 v 21 mw v dd = 12 v, v ss = ?12 v, v cc = 5 v full shutdown mode 38.25 w v dd = 16.5 v, v ss = ?16.5 v, v cc = 5.25 v 1 temperature range is ?40c to +85c. 2 see the terminology section. 3 sample tested during initial release to ensure compliance. 4 for dc accuracy specifications, the lsb si ze for differential mode is fsr/8192. for single-ended mode/pse udo differential mode , the lsb size is fsr/4096, unless otherwise noted. 5 unipolar 0 v to 10 v range with straight binary output coding. 6 bipolar range with twos complement output coding.
ad7329 rev. a | page 7 of 40 timing specifications v dd = 12 v to 16.5 v, v ss = ?12 v to ?16.5 v, v cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v, v ref = 2.5 v internal/external, t a = t max to t min . timing specifications apply with a 32 pf load, unless otherwise noted. mux out + is connected directly to adc in + and mux out ? is connected directly to adc in ?, which is connected to gnd for single-ended mode. table 3. limit at t min , t max description parameter v cc < 4.75 v v cc = 4.75 v to 5.25 v unit v drive v cc f sclk 50 50 khz min 14 20 mhz max t convert 16 t sclk 16 t sclk ns max t sclk = 1/f sclk t quiet 75 60 ns min minimum time between end of serial read and next falling edge of cs t 1 12 5 ns min minimum cs pulse width t 2 1 25 20 ns min cs to sclk setup time; bipolar input ranges (10 v, 5 v, 2.5 v) 45 35 ns min unipolar input range (0 v to 10 v) t 3 26 14 ns max delay from cs until dout three-state disabled t 4 57 43 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 7 13 8 ns min sclk to data valid hold time t 8 40 22 ns max sclk falling edge to dout high impedance 10 9 ns min sclk falling edge to dout high impedance t 9 4 4 ns min din setup time prior to sclk falling edge t 10 2 2 ns min din hold time after sclk falling edge t power-up 750 750 ns max power-up from autostandby 500 500 s max power-up from full shutdown/autoshutdown mode, internal reference 25 25 s typ power-up from full shutdown/autoshutdown mode, external reference 1 when using v cc = 4.75 v to 5.25 v and the 0 v to 10 v unipolar range, running at 1 msps throughput rate with t 2 at 20 ns, the mark-space ratio must be limited to 50:50. add1 1 2 3 4 5 13 14 15 16 write reg sel1 reg sel2 lsb 0 msb add0 sign db11 db10 db2 db1 db0 t 2 t 6 t 4 t 9 t 10 t 3 t 7 t 5 t 8 t 1 t quiet t convert sclk cs dout three- state three-state din add2 3 identification bits 05402-002 figure 2. serial interface timing diagram
ad7329 rev. a | page 8 of 40 absolute maximum ratings t a = 25c, unless otherwise noted table 4. parameter rating v dd to agnd, dgnd ?0.3 v to +16.5 v v ss to agnd, dgnd +0.3 v to ?16.5 v v dd to v cc v cc ? 0.3 v to +16.5 v v cc to agnd, dgnd ?0.3 v to +7 v v drive to agnd, dgnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v analog input voltage to agnd 1 v ss ? 0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to +7 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v ref in to agnd ?0.3 v to v cc + 0.3 v input current to any pin except supplies 2 10 ma operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tssop package ja thermal impedance 128c/w jc thermal impedance 42c/w pb-free temperature, soldering reflow 260(0)c esd 2.5 kv 1 if the analog inputs are driven from alternative v dd and v ss supply circuitry, schottky diodes should be placed in series with the v dd and v ss supplies of the ad7329 (see the power supp ly configurati on section). 2 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7329 rev. a | page 9 of 40 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 din dgnd agnd adc in + v ss ref in /ref out cs dgnd dout v drive adc in ? v dd v cc mux out + v in 0 v in 5 v in 4 v in 1 mux out ? v in 2 v in 7 v in 6 v in 3 sclk ad7329 top view (not to scale) 05402-003 figure 3. tssop pin configuration table 5. pin function descriptions pin no. mnemonic descriptions 24 sclk serial clock, logic input. a serial clock input provides the sclk used for accessing the data from the ad7329. this clock is also used as the clock source for the conversion process. 22 dout serial data output. the conversion o utput data is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input, an d 16 sclks are required to access the data. the data stream consists of three channel identi fication bits, the sign bit, and 12 bi ts of conversion data. the data is provided msb first (see the serial interface section). 1 cs chip select. active low logic input. this input provid es the dual function of initiating conversions on the ad7329 and frames the serial data transfer. 2 din data in. data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of sclk (see the registers section). 21 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. this pin should be decoupled to dgnd. the voltag e at this pin can be different than that at v cc but should not exceed v cc by more than 0.3 v. 3, 23 dgnd digital ground. ground reference point for all digita l circuitry on the ad7329. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 4 agnd analog ground. ground reference point for all analog circuitry on the ad7329. all analog input signals and any external reference signal should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the same potential and must not be mo re than 0.3 v apart, even on a transient basis. 5 ref in /ref out reference input/reference output. the on-chip reference is available on this pin for use external to the ad7329. the nominal internal reference voltage is 2.5 v, which ap pears at the pin. a 680 nf capacitor should be placed on the reference pin. alternatively, the internal reference can be disabled and an external reference can be applied to this input. on power-up, the external reference mode is the default condition (see the reference section). 20 v cc analog supply voltage, 2.7 v to 5.25 v. this is the su pply voltage for the adc core on the ad7329. this supply should be decoupled to agnd. 19 v dd positive power supply voltage. this is the positi ve supply voltage for the analog input section. 6 v ss negative power supply voltage. this is the nega tive supply voltage for the analog input section. 7 adc in + positive adc input. this pin allows access to the on-chip track-and-hold. the voltage applied to this pin is still a high voltage signal (10 v, 5 v, 2.5 v, or 0 v to +10 v). 8 mux out + positive multiplexer output. the output of the multiplexer ap pears at this pin. the voltage at this pin is still a high voltage signal equivalent to the voltage applied to the v in + input channel, as selected in the control register or sequence register. if no external filtering or buffering is required, this pin should be tied to the adc in + pin.
ad7329 rev. a | page 10 of 40 pin no. mnemonic descriptions 17 mux out ? negative multiplexer output. this pin allows access to the on-chip track-and-hold. the voltage applied to this pin is still a high voltage signal when the ad7329 is in differential mode. when the ad7329 is in single-ended mode, this signal is agnd, and mux out ? can be connected directly to the adc in ? pin. when the ad7329 is in pseudo differential mode, a small dc voltage appears at this pin, and this pin should be tied to the adc in ? pin. 18 adc in ? negative adc input. this pin allows access to the tr ack-and-hold. when the ad7329 is in single-ended mode, this pin can be tied to mux out ?, which is connected to agnd. when the ad7329 is in pseudo differential mode, this pin should be connected to mux out ?. when the ad7329 is in true differential mode, the voltage applied to this pin is a high voltage signal (10 v, 5 v, 2.5 v, or 0 v to +10 v). 9, 10, 16, 15, 11, 12, 14, 13 v in 0 to v in 7 analog input 0 through analog input 7. the analog in puts are multiplexed into the on-chip track-and-hold. the analog input channel for conversion is selected by programming the channel address bits, add2 through add0, in the control register. the inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. the configuration of the analog inputs is selected by programming the mo de bits, mode 1 and mode 0, in the control register. the input range on each input channel is controlled by programming the range registers. input ranges of 10 v, 5 v, 2.5 v, or 0 v to +10 v can be selected on each analog input channel (see the range registers section). on power up, v in 0 is automatically selected and the voltage on this pin appears on mux out +.
ad7329 rev. a | page 11 of 40 typical performance characteristics 1.0 ?1.0 0 8192 code inl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 v cc = v drive = 5v t a = 25c v dd = 15v, v ss = ?15v int/ext 2.5v reference 10v range +inl = +0.55lsb ?inl = ?0.68lsb 05402-007 0 ?140 0 500 frequency (khz) snr (db) ?20 ?40 ?60 ?80 ?100 ?120 50 100 150 200 250 300 350 400 450 4096 point fft v cc = v drive = 5v v dd = 15v, v ss = ?15v t a = 25c int/ext 2.5v reference 10v range f in = 50khz snr = 77.30db sinad = 76.85db thd = ?86.96db sfdr = ?88.22db 05402-004 figure 7. typical inl for true differential mode figure 4. fft for true differential mode 1.0 ?1.0 0 8192 code dnl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 v cc = v drive = 5v t a = 25c v dd = 15v, v ss = ?15v int/ext 2.5v reference 10v range +dnl = +0.79lsb ?dnl = ?0.38lsb 05402-008 0 ?140 0 500 frequency (khz) snr (db) ?20 ?40 ?60 ?80 ?100 ?120 50 100 150 200 250 300 350 400 450 4096 point fft v cc = v drive = 5v v dd = 15v, v ss = ?15v t a = 25c int/ext 2.5v reference 10v range f in = 50khz snr = 74.67db sinad = 74.03db thd = ?82.68db sfdr = ?85.40db 05402-005 figure 8. typical dnl for single-ended mode figure 5. fft for single-ended mode 1.0 ?1.0 0 8192 code inl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 v cc = v drive = 5v t a = 25c v dd = 15v, v ss = ?15v int/ext 2.5v reference 10v range +inl = +0.87lsb ?inl = ?0.49lsb 05402-009 1.0 ?1.0 0 8192 code dnl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 v cc = v drive = 5v t a = 25c v dd = 15v, v ss = ?15v int/ext 2.5v reference 10v range +dnl = +0.72lsb ?dnl = ?0.22lsb 05402-006 figure 9. typical inl for single-ended mode figure 6. typical dnl for true differential mode
ad7329 rev. a | page 12 of 40 ? 50 ?95 10 1000 05402-010 analog input frequency (khz) thd (db) 2.5v range 0v to +10v range 10v range 5v range v cc = v drive = 5v v dd = 12v, v ss = ?12v t a = 25c f s = 1msps internal reference ad8021 between mux out+ and adc in+ pins 100 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 figure 10. thd vs. analog input frequency for single-ended mode at 5 v v cc ? 50 ?95 10 1000 05402-011 analog input frequency (khz) thd (db) 2.5v range 0v to +10v range 10v range 5v range v cc = v drive = 5v v dd = 12v, v ss = ?12v t a = 25c f s = 1msps internal reference ad8021 between mux out and adc in pins 100 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 figure 11. thd vs. analog input frequency for true differential mode at 5 v v cc 74 66 10 1000 05402-012 analog input frequency (khz) sinad (db) 2.5v range 0v to +10v range 10v range 5v range v cc = v drive = 5v v dd = 12v, v ss = ?12v t a = 25c f s = 1msps internal reference ad8021 between mux out+ and adc in+ pins 73 72 71 70 69 68 67 100 figure 12. sinad vs. analog input frequency for single-ended mode at 5 v v cc sinad (db) 75 80 50 10 1000 05402-013 analog input frequency (khz) 2.5v range 0v to +10v range 10v range 5v range v cc = v drive = 5v v dd = 12v, v ss = ?12v t a = 25c f s = 1msps internal reference ad8021 between mux out and adc in pins 100 70 65 60 55 figure 13. sinad vs. analog input frequency for true differential mode at 5 v v cc ? 50 ?100 0 600 05402-014 frequency of input noise (khz) channel-to-channel isolation (db) 100 200 300 400 500 v dd = 12v, v ss = ?12v v cc = v drive = 5v single-ended mode 50khz on selected channe l f s = 1msps t a = 25c wire link with ad8021 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 figure 14. channel-to-channel isolation with and without ad8021 between the mux out + and adc in + pins 10k 0 ?2 code number of occurrences 9k 8k 7k 6k 5k 4k 3k 2k 1k ?1 0 1 2 0 228 9469 303 0 v cc = 5v v dd = 12v, v ss = ?12v range = 10v 10k samples t a = 25c 05402-015 figure 15. histogram of codes, true differential mode
ad7329 rev. a | page 13 of 40 8k 0 ?3 code number of occurrences 7k 6k 5k 4k 3k 2k 1k ?2?10123 v cc = 5v v dd = 12v, v ss = ?12v range = 10v 10k samples t a = 25c 023 1201 7600 1165 11 0 05402-016 figure 16. histogram of codes, single-ended mode ? 50 ?100 0 ripple frequency (khz) cmrr (db) ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 200 400 600 800 1000 1200 differential mode f in = 50khz v dd = 12v, v ss = ?12v f s = 1msps t a = 25c v cc = 5v v cc = 3v 05402-017 figure 17. cmrr vs. common-mode ripple frequency 2.0 ?2.0 supply voltage (v) (v dd = +, v ss = ?) dnl error (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 5 7 9 11 13 15 17 19 5v range v cc = v drive = 5v internal reference single-ended mode ad8021 between mux out + and adc in + pins dnl = 500ksps dnl = 500ksps dnl = 1msps dnl = 1msps 05402-018 figure 18. dnl error vs. supply voltage at 500 ksps and 1 msps 2.0 ?2.0 supply voltage (v) (v dd = +, v ss = ?) inl error (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 5 7 9 11 13 15 17 19 5v range v cc = v drive = 5v internal reference single-ended mode ad8021 between mux out + and adc in + pins inl = 1msps inl = 1msps inl = 500ksps inl = 500ksps 05402-019 figure 19. inl error vs. supply voltage at 500 ksps and 1 msps ? 50 ?100 0 1200 supply ripple frequency (khz) psrr (db) ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 200 400 600 800 1000 100mv p-p sine wave on each supply no decoupling single-ended mode f s = 1msps v cc = 5v v cc = 3v v dd = 12v v ss = ?12v 05402-020 figure 20. psrr vs. supply ripple frequency without supply decoupling ? 50 ?100 10 1000 05402-021 analog input frequency (khz) thd (db) differential mode v dd = 12v, v ss = ?12v v cc = v drive = 5v internal reference ad8021 between mux out and adc in pins 100 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 r in = 2000 ? r in = 1000 ? r in = 600 ? r in = 100 ? r in = 50 ? 10v range r in = 4000 ? r in = 1000 ? r in = 600 ? r in = 100 ? r in = 50 ? 2.5v range figure 21. thd vs. analog input frequency for various source impedances, true differential mode
ad7329 rev. a | page 14 of 40 ? 76 ?88 5 17 05402-055 supply voltage (v) (v dd = +, v ss =?) thd (db) 30khz/1msps 10khz/1msps 30khz/500ksps 10khz/500ksps 5v range v cc = v drive = 5v internal reference single-ended mode ad8021 between mux out + and adc in + pins ?78 ?80 ?82 ?84 ?86 7 9 11 13 15 ? 50 ?90 10 1000 05402-022 analog input frequency (khz) thd (db) single-ended mode v dd = 12v, v ss = ?12v v cc = v drive = 5v internal reference ad8021 between mux out + and adc in + pins 100 r in = 2000 ? r in = 1000 ? r in = 600 ? r in = 100 ? r in = 50 ? 2.5v range r in = 2000 ? r in = 1000 ? r in = 600 ? r in = 100 ? r in = 50 ? 10v range ?55 ?60 ?65 ?70 ?75 ?80 ?85 figure 23. thd vs. supply voltage at 500 ksps and 1 msps with 10 khz and 30 khz input tone figure 22. thd vs. analog input frequency for various source impedances, single-ended mode
ad7329 rev. a | page 15 of 40 terminology differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale (a point 1 lsb below the first code transition) and full scale (a point 1 lsb above the last code transition). offset error this applies to straight binary output coding. it is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, agnd + 1 lsb. offset error match this is the difference in offset error between any two input channels. gain error this applies to straight binary output coding. it is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 4 v ref ? 1 lsb, 2 v ref ? 1 lsb, v ref ? 1 lsb) after adjusting for the offset error. gain error match this is the difference in gain error between any two input channels. bipolar zero code error this applies when using twos complement output coding and a bipolar analog input. it is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, agnd ? 1 lsb. bipolar zero code error match this refers to the difference in bipolar zero code error between any two input channels. positive full-scale error this applies when using twos complement output coding and any of the bipolar analog input ranges. it is the deviation of the last code transition (011 110) to (011 111) from the ideal (that is, 4 v ref ? 1 lsb, 2 v ref ? 1 lsb, v ref ? 1 lsb) after adjusting for the bipolar zero code error. positive full-scale error match this is the difference in positive full-scale error between any two input channels. negative full-scale error this applies when using twos complement output coding and any of the bipolar analog input ranges. this is the deviation of the first code transition (10 000) to (10 001) from the ideal (that is, ?4 v ref + 1 lsb, ?2 v ref + 1 lsb, ?v ref + 1 lsb) after adjusting for the bipolar zero code error. negative full-scale error match this is the difference in negative full-scale error between any two input channels. track-and-hold acquisition time the track-and-hold amplifier returns to track mode after the 14 th sclk rising edge. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ? lsb, after the end of a conversion. signal-to-noise-and-distortion ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process. the more levels, the smaller the quantization noise. theoretically, the signal-to-noise-and-distortion ratio for an ideal n-bit converter with a sine wave input is given by signal to ( noise + distortion ) = (6.02 n + 1.76) db for a 13-bit converter, this is 80.02 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7329, it is defined as 1 65432 v vvvvv thd 22222 log20)db( ++++ = where v 1 is the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak.
ad7329 rev. a | page 16 of 40 channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full-scale, 100 khz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 khz signal. figure 14 shows the worst case across all eight channels for the ad7329. the analog input range is programmed to be 2.5 v on the selected channel and 10 v on all other channels. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second-order terms include (fa + fb) and (fa ? fb), whereas the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7329 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. power supply rejection (psr) variations in power supply affect the full-scale transition but not the linearity of the converter. power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see the typical performance characteristics section). common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv sine wave applied to the common-mode voltage of the v in + and v in ? frequency, f s , as cmrr (db) = 10 log ( pf / pf s ) where pf is the power at frequency f in the adc output, and pf s is the power at frequency f s in the adc output (see figure 17 ).
ad7329 rev. a | page 17 of 40 theory of operation circuit information the ad7329 is a fast, 8-channel, 12-bit plus sign, bipolar input, serial adc. the ad7329 can accept bipolar input ranges that include 10 v, 5 v, and 2.5 v; it can also accept a 0 v to +10 v unipolar input range. a different analog input range can be programmed on each analog input channel via the on-chip registers. the ad7329 has a high speed serial interface that can operate at throughput rates up to 1 msps. the ad7329 requires v dd and v ss dual supplies for the high voltage analog input structures. these supplies must be equal to or greater than the analog input range. see table 6 for the requirements of these supplies for each analog input range. the ad7329 requires a low voltage 2.7 v to 5.25 v v cc supply to power the adc core. table 6. reference and supply requirements for each analog input range selected analog input range (v) reference voltage (v) full-scale input range (v) v cc (v) minimum v dd /v ss (v) 10 2.5 10 3/5 10 3.0 12 3/5 12 5 2.5 5 3/5 5 3.0 6 3/5 6 2.5 2.5 2.5 3/5 5 3.0 3 3/5 5 0 to +10 2.5 0 to +10 3/5 +10/agnd 3.0 0 to +12 3/5 +12/agnd to meet the performance specifications when the ad7329 is configured with the minimum v dd and v ss supplies for a chosen analog input range, the throughput rate should be decreased from the maximum throughput range (see the typical performance characteristics section). the analog inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. selection can be made by pro- gramming the mode bits, mode 0 and mode 1, in the control register. the serial clock input accesses data from the part and provides the clock source for the successive approximation adc. the ad7329 has an on-chip 2.5 v reference. however, the ad7329 can also work with an external reference. on power-up, the external reference operation is the default option. if the internal reference is the preferred option, the user must write to the reference bit in the control register to select the internal reference operation. the ad7329 also features power-down options to allow power savings between conversions. the power-down modes are selected by programming the on-chip control register as described in the modes of operation section. converter operation the ad7329 is a successive approximation analog-to-digital converter built around two capacitive dacs. figure 24 and figure 25 show simplified schematics of the adc in single- ended mode during the acquisition and conversion phases, respectively. figure 26 and figure 27 show simplified schematics of the adc in differential mode during acquisition and conversion phases, respectively. in both examples, the mux out + pin is connected to the adc in + pin, and the mux out ? pin is connected to the adc in ? pin. the adc is composed of control logic, a sar, and capacitive dacs. in figure 24 (the acquisition phase), sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input. capacitive dac control logic comparator agnd sw2 sw1 a b c s v in 0 05402-023 figure 24. adc configuration during ac quisition phase, single-ended mode when the adc starts a conversion ( figure 25 ), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and the charge redistribution dac are used to add and subtract fixed amounts of charge from the capacitive dac to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code capacitive dac control logic comparator agnd sw2 sw1 a b c s v in 0 05402-024 figure 25. adc configuration during conversion phase, single-ended mode
ad7329 rev. a | page 18 of 40 figure 26 shows the differential configuration during the acquisition phase. for the conversion phase, sw3 opens and sw1 and sw2 move to position b (see figure 27 ). the output impedances of the source driving the v in + and v in ? pins must match; otherwise, the two inputs have different settling times, resulting in errors. capacitive dac control logic capacitive dac comparator sw3 sw1 a b c s c s v in + sw2 a b v in ? v ref 05402-025 figure 26. adc configuration during acquisition phase, differential mode capacitive dac control logic capacitive dac comparator sw3 sw1 a b c s c s v in + sw2 a b v in ? v ref 05402-026 figure 27. adc configuration during conversion phase, differential mode output coding the ad7329 default output coding is set to twos complement. the output coding is controlled by the coding bit in the control register. to change the output coding to straight binary coding, the coding bit in the control register must be set. when operating in sequence mode, the output coding for each channel in the sequence is the value written to the coding bit during the last write to the control register. transfer functions the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb, and so on). the lsb size is dependent on the analog input range selected. table 7. lsb sizes for each analog input range input range full-scale range/8192 codes lsb size 10 v 20 v 2.441 mv 5 v 10 v 1.22 mv 2.5 v 5 v 0.61 mv 0 v to +10 v 10 v 1.22 mv the ideal transfer characteristic for the ad7329 when twos complement coding is selected is shown in figure 28 . the ideal transfer characteristic for the ad7329 when straight binary coding is selected is shown in figure 29 . 011 ... 111 011 ... 110 000 ... 001 000 ... 000 111 ... 111 ?fsr/2 + 1lsb agnd + 1lsb +fsr/2 ? 1lsb bipolar ranges +fsr ? 1lsb unipolar range agnd ? 1lsb analog input adc code 100 ... 010 100 ... 001 100 ... 000 05402-027 figure 28. twos complement transfer characteristic, bipolar ranges 111 ... 111 111 ... 110 111 ... 000 011 ... 111 ?fsr/2 + 1lsb agnd + 1lsb +fsr/2 ? 1lsb bipolar ranges +fsr ? 1lsb unipolar range analog input adc code 000 ... 010 000 ... 001 000 ... 000 05402-028 figure 29. straight binary transfer characteristic, bipolar ranges analog input structure the analog inputs of the ad7329 can be configured as single- ended, true differential, or pseudo differential via the control register mode bits, as shown in table 12 . the ad7329 can accept true bipolar input signals. on power-up, the analog inputs operate as eight single-ended analog input channels. if true differential or pseudo differential is required, a write to the control register is necessary after power-up to change this configuration. figure 30 shows the equivalent analog input circuit of the ad7329 in single-ended mode. figure 31 shows the equivalent analog input structure in differential mode. the two diodes provide esd protection for the analog inputs. d d v dd adc in + mux out + c2 r1 v in 0 v ss c1 c3 c4 05402-029 figure 30. equivalent analog in put circuit, single-ended mode
ad7329 rev. a | page 19 of 40 d d v dd adc in ? mux out ? c2 r1 v in ? v ss c1 c3 c4 05402-030 d d v dd adc in + mux out + c2 r1 v in + v ss c1 c3 c4 figure 31. equivalent analog input circuit, differential mode care should be taken to ensure that the analog input does not exceed the v dd and v ss supply rails by more than 300 mv. exceeding this value causes the diodes to become forward biased and to start conducting into either the v dd supply rail or the v ss supply rail. these diodes can conduct up to 10 ma without causing irreversible damage to the part. in figure 30 and figure 31 , capacitor c1 is typically 4 pf and can primarily be attributed to pin capacitance. resistor r1 is a lumped component made up of the on resistance of the input multiplexer and the track-and-hold switch. capacitor c2 is the sampling capacitor; its capacitance varies depending on the analog input range selected (see the specifications section). track-and-hold section the track-and-hold on the analog input of the ad7329 allows the adc to accurately convert an input sine wave of full-scale amplitude to 13-bit accuracy. the input bandwidth of the track- and-hold is greater than the nyquist rate of the adc. the ad7329 can handle frequencies up to 20 mhz. the adc in pins connect directly to the input stage of the track- and-hold circuit. this is a high impedance input. connecting the mux out pins directly to the adc in pins connects the multiplexer output to the track-and-hold circuit. the input voltage range on the adc in pins is determined by the range register bits for the input channel selected. the user must ensure that the input voltage to the adc in pins is within the selected voltage range. the track-and-hold enters its tracking mode on the 14 th sclk rising edge after the cs falling edge. the time required to acquire an input signal depends on how quickly the sampling capacitor is charged. with zero source impedance, 300 ns is sufficient to acquire the signal to the 13-bit level. the acquisition time required is calculated using the following formula: t acq = 10 (( r source + r)c) where c is the sampling capacitance, and r is the resistance seen by the track-and-hold amplifier looking at the input. for the ad7329, the value of r includes the on resistance of the input multiplexer and is typically 300 . r source should include any extra source impedance on the analog input. the ad7329 enters track mode on the 14 th sclk rising edge. when the ad7329 is run at a throughput rate of 1 msps with a 20 mhz sclk signal, the adc has approximately 1.5 sclk periods plus t 8 and the quiet time, t quiet , to acquire the analog input signal. the adc goes back into hold mode on the cs falling edge. the current required to drive the adc is extremely small when using the external op amp between the mux out and adc in pins. this is due to the high input impedance of the op amp placed between the mux out and adc in pins. this can be seen in figure 32 , where the current required to drive the ad7329 input is <0.2 a when ad8021 is placed between the mux out and adc in pins. 0.20 0.14 0 1000 05402-056 throughput rate (ksps) input current (a) 0.19 0.18 0.17 0.16 0.15 100 200 300 400 500 600 700 800 900 v dd = 12v, v ss = ?12v v cc = v drive = 5v single-ended mode 50khz on selected channel f in = 50khz t a = 25c ad8021 between mux out and adc in pins figure 32. input current vs. throughput rate with ad8021 between mux out and adc in 35 0 0 1000 05402-057 throughput rate (ksps) input current (a) 100 200 300 400 500 600 700 800 900 v dd = 12v, v ss = ?12v v cc = v drive = 5v single-ended mode 50khz on selected channel f in = 50khz t a = 25c wire link between mux out and adc in pins 30 25 20 15 10 5 figure 33. input current vs. throughput rate with a wire link between mux out and adc in
ad7329 rev. a | page 20 of 40 typical connection diagram figure 34 shows a typical connection diagram for the ad7329. in this configuration, the agnd pin is connected to the analog ground plane of the system, and the dgnd pin is connected to the digital ground plane of the system. the analog inputs on the ad7329 can be configured to operate in single-ended, true differential, or pseudo differential mode. the ad7329 can operate with either an internal or external reference. in figure 34 , the ad7329 is configured to operate with the internal 2.5 v reference. a 680 nf decoupling capacitor is required when operating with the internal reference. the v cc pin can be connected to either a 3 v or a 5 v supply voltage. the v dd and v ss are the dual supplies for the high voltage analog input structures. the voltage on these pins must be equal to or greater than the highest analog input range selected on the analog input channels (see tabl e 6 for more information). the v drive pin is connected to the supply voltage of the microprocessor. the voltage applied to the v drive input controls the voltage of the serial interface. ad7329 v cc v dd 1 serial interface filtering/buffering c/p v in 0 v in 1 v in 2 v in 3 v in 4 v in 5 v in 6 v in 7 ref in /ref out cs dout v drive sclk din dgnd 10f 0.1f + mux out + adc in + mux out ? adc in ? 10f 0.1f + 10f 0.1f + analog inputs: 10v, 5v, 2.5v, 0v to +10v + 15v ? 15v 680nf v ss 1 v cc +2.7v to +5.25 v 1 minimum v dd and v ss supply voltages depend on the highest analog input range selected. agnd 05402-031 10f 0.1f + +3v supply figure 34. typical connection diagram, single-ended mode ad7329 v cc v dd 1 serial interface filtering/buffering c/p v in 0 v in 1 v in 2 v in 3 v in 4 v in 5 v in 6 v in 7 ref in /ref out cs dout v drive sclk din dgnd 10f 0.1f + mux out ? mux out + adc in ? adc in + 10f 0.1f + 10f 0.1f analog inputs: 10v, 5v, 2.5v, 0v to +10v + 15 v ?15v 680nf v ss 1 v cc +2.7v to +5.25 v 1 minimum v dd and v ss supply voltages depend on the highest analog input range selected. agnd 05402-032 10f 0.1f + +3v supply + figure 35. typical connection diagram, differential mode analog input single-ended inputs the ad7329 has a total of eight analog inputs when operating in single-ended mode. each analog input can be independently programmed to one of the four analog input ranges. in applications where the signal source is high impedance, it is recommended to buffer the signal before applying it to the adc analog inputs. figure 36 shows the configuration of the ad7329 in single- ended mode. ad7329 1 v in + v + v? v dd v ss v cc 5 v agnd 1 additional pins omitted for clarity. 0 5402-033 figure 36. single-ended mode typical connection diagram true differential mode the ad7329 can have four true differential analog input pairs. differential signals have some benefits over single-ended signals, including better noise immunity based on the devices common-mode rejection and improvements in distortion performance. figure 37 defines the configuration of the true differential analog inputs of the ad7329. ad7329 1 v in + v in ? 1 additional pins omitted for clarity. 05402-034 figure 37. true differential inputs the amplitude of the differential signal is the difference between the signals applied to the v in + and v in ? pins in each differential pair (v in + ? v in ?). v in + and v in ? should be simultaneously driven by two signals of equal amplitude, dependent on the input range selected, that are 180 out of phase. assuming the 4 v ref mode, the amplitude of the differential signal is ?20 v to +20 v p-p (2 4 v ref ), regardless of the common mode. the common mode is the average of the two signals ( v in + + v in ? )/2 and is therefore the voltage on which the two input signals are centered.
ad7329 rev. a | page 21 of 40 this voltage is set up externally, and its range varies with reference voltage. as the reference voltage increases, the common-mode range decreases. when the differential inputs are driven with an amplifier, the actual common-mode range is determined by the amplifiers output swing. if the differential inputs are not driven from an amplifier, the common-mode range is determined by the supply voltage on the v dd supply pin and the v ss supply pin. when a conversion takes place, the common mode is rejected, resulting in a noise-free signal of amplitude ?2 (4 v ref ) to +2 (4 v ref ), corresponding to digital codes ?4096 to +4095. 16.5v v dd /v ss 12v v dd /v ss 5 ?6 v com range (v) 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 v cc = 3v v ref = 3v 2.5v range 10v range 5v range 2.5v range 5v range 10v range 05402-035 figure 38. common-mode range for v cc = 3 v and ref in /ref out = 3 v 16.5v v dd /v ss 12v v dd /v ss v com range (v) v cc = 5v v ref = 3v 8 ?4 6 4 2 0 ?2 2.5v range 10v range 5v range 2.5v range 5v range 10v range 05402-036 figure 39. common-mode range for v cc = 5 v and ref in /ref out = 3 v 6 ?8 4 2 0 ?2 ?4 ?6 16.5v v dd /v ss 12v v dd /v ss v com range (v) v cc = 3v v ref = 2.5v 2.5v range 10v range 5v range 2.5v range 5v range 10v range 05402-037 figure 40. common-mode range for v cc = 3 v and ref in /ref out = 2.5 v 8 ?8 6 4 2 0 ?2 ?4 ?6 05402-038 16.5v v dd /v ss 12v v dd /v ss v com range (v) v cc = 5v v ref = 2.5v 2.5v range 10v range 5v range 2.5v range 5v range 10v range figure 41. common-mode range for v cc = 5 v and ref in /ref out = 2.5 v
ad7329 rev. a | page 22 of 40 pseudo differential inputs the ad7329 can have four pseudo differential pairs or seven pseudo differential inputs referenced to a common v in ? pin. the v in + inputs are coupled to the signal source and must have an amplitude within the selected range for that channel, as programmed in the range register. a dc input is applied to the v in ? pin. the voltage applied to this input provides an offset for the v in + input from ground or pseudo ground. pseudo differential inputs separate the analog input signal ground from the adc ground, allowing cancellation of dc common-mode voltages. figure 42 shows the configuration of the ad7329 in pseudo differential mode. when a conversion takes place, the pseudo ground corresponds to code ?4096 and the maximum amplitude corresponds to code +4095. ad7329 1 v in + v + v? v dd v ss v cc 5 v 1 additional pins omitted for clarity. v in ? 0 5402-039 figure 42. pseudo differential inputs figure 43 and figure 44 show the typical voltage range on the v in ? pin for various analog input ranges when configured in the pseudo differential mode. for example, when the ad7329 is configured to operate in pseudo differential mode and the 5 v range is selected with 16.5 v v dd , ?16.5 v v ss , and 5 v v cc , the voltage on the v in ? pin can vary from ?6.5 v to +6.5 v. 05402-040 8 ?8 6 4 2 0 ?2 ?4 ?6 2.5v range 10v range 10v range 5v range 2.5v range 5v range 0v to +10v range 0v to +10v range 16.5v v dd /v ss 12v v dd /v ss v cc = 5v v ref = 2.5v figure 43. pseudo differential input range with v cc = 5 v 05402-041 2.5v range 10v range 10v range 5v range 2.5v range 5v range 0v to +10v range 0v to +10v range 16.5v v dd /v ss 12v v dd /v ss 4 ? 8 2 0 ? 2 ? 4 ? 6 v cc = 3v v ref = 2.5v figure 44. pseudo differential input range with v cc = 3 v
ad7329 rev. a | page 23 of 40 driver amplifier choice in applications where the harmonic distortion and signal-to- noise ratio are critical specifications, the analog input of the ad7329 should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc and can necessitate the use of an input buffer amplifier. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be tolerated in the application. the thd increases as the source impedance increases and performance degrades. figure 21 and figure 22 show graphs of the thd vs. the analog input frequency for various source impedances. depending on the input range and analog input configuration selected, the ad7329 can handle source impedances of up to 4 k before the thd starts to degrade. due to the programmable nature of the analog inputs on the ad7329, the choice of op amp used to drive the inputs is a function of the particular application and depends on the input configuration and the analog input voltage ranges selected. the driver amplifier must be able to settle for a full-scale step to a 13-bit level, within 0.0122%, in less than the specified acquisition time of the ad7329. an op amp such as the ad8021 meets this requirement when operating in single-ended mode. the ad8021 needs an external compensating npo type of capacitor. the ad8022 can also be used in high frequency applications where a dual version is required. for lower frequency applications, op amps such as the ad797, ad845 , and ad8610 can be used with the ad7329 in single-ended mode configuration. table 8. typical ac performance using different op amps in single-ended mode, 10 v input range parameter no buffer ad845 ad8021 ad8610 snr (db) 74.24 74.03 73.78 73.88 snrd (db) 72.42 74.88 72.11 71.98 thd (db) ?77.05 ?75.95 ?77.04 ?76.47 table 9. typical ac performance using different op amps in differential mode, 10 v input range parameter no buffer ad845 ad8021 ad8610 snr (db) 77.16 76.81 76.95 76.76 snrd (db) 76.50 76.02 76.78 75.89 thd (db) ?84.91 ?83.74 ?90.55 ?83.24 differential operation requires that v in + and v in ? be simulta- neously driven with two signals of equal amplitude that are 180 out of phase. the common mode must be set up externally to the ad7329. the common-mode range is determined by the ref in / ref out voltage, the v cc supply voltage, and the particular amplifier used to drive the analog inputs. differential mode with either an ac input or a dc input provides the best thd performance over a wide frequency range. because not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. this single-ended-to-differential conversion can be performed using an op amp pair. typical connection diagrams for an op amp pair are shown in figure 45 and figure 46 . in figure 45 , the common-mode signal is applied to the noninverting input of the second amplifier.
ad7329 rev. a | page 24 of 40 v in v+ v? 2k? 1.5k ? 1.5k ? 1.5k ? 1.5k ? 10k? 05402-042 1.5k ? 7 4 5 2 6 3 mux out + 100nf 10pf adc in + v dd v ss ad8021 100nf 05402-058 figure 45. single-ended-to-differential configuration with the ad845 for bipolar operation figure 47. ad8021 configuration used between mux out and adc in pins v in v+ v? 442? 442? 442? 442? 442? 100 ? ad8021 ad8021 442 ? 05402-043 figure 46. single-ended-to-differential configuration with the ad8021
ad7329 rev. a | page 25 of 40 registers the ad7329 has four programmable registers: the control register, sequence register, range register 1, and range register 2. these registers are write-only registers. addressing registers a serial transfer on the ad7329 consists of 16 sclk cycles. the three msbs on the din line during the 16 sclk transfer are deco ded to determine which register is addressed. the three msbs consist of the write bit, register select 1 bit, and register select 2 bi t. the register select bits are used to determine which of the four on-board registers is selected. the write bit determines if the data on the din line following the register select bits loads into the addressed register. if the write bit is 1, the bits load into the register ad dressed by the register select bits. if the write bit is 0, the data on the din line does not load into any register. table 10. decoding register select bits and write bit write register select 1 register select 2 description 0 0 0 data on the din line during this serial transfer is ignored. 1 0 0 this combination selects the control register. the subsequent 12 bits are loaded into the control register. 1 0 1 this combination selects range register 1. the subsequent 8 bits are loaded into range register 1. 1 1 0 this combination selects range register 2. the subsequent 8 bits are loaded into range register 2. 1 1 1 this combination selects the sequence register. the subsequent 8 bits are loaded into the sequence register.
ad7329 rev. a | page 26 of 40 control register the control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. the control register is a write-only, 12-bit register. data loaded on the din line corresponds to the ad7329 configuration for the next conversion. if the sequence register is being used, data should be loaded into the control register after the range registers a nd the sequence register have been initialized. the bit functions of the control register are described in table 11 (the power-up status of all bits is 0). msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write register select 1 register select 2 add2 add1 add0 mode 1 mode 0 pm1 pm0 coding ref seq1 seq2 weak/ three-state 0 table 11. control register details bit mnemonic description 12, 11, 10 add2, add1, add0 these three channel address bits are used to select th e analog input channel for the next conversion if the sequencer is not being used. if the sequencer is bein g used, the three channel address bits are used to select the final channel in a consecutive sequence. 9, 8 mode 1, mode 0 these two mode bits are used to select the co nfiguration of the eight analog input pins, v in 0 to v in 7. these pins are used in conjunction with the channel address bits. on the ad7329, the analog inputs can be configured as eight single-ended inputs, four fully diff erential input pairs, four pseudo differential inputs, or seven pseudo differential inputs (see table 12 ). 7, 6 pm1, pm0 the power management bits are used to select different power mode options on the ad7329 (see table 13 ). 5 coding this bit is used to select the type of output coding that the ad7329 uses for the next conversion result. if coding = 0, the output coding is twos complement. if coding = 1, the output coding is straight binary. when operating in sequence mode, the output coding fo r each channel is the value written to the coding bit during the last write to the control register. 4 ref the reference bit is used to enable or disable the internal reference. if ref = 0, the external reference is enabled and used for the next conversion and the internal reference is disabled. if ref = 1, the internal ref- erence is used for the next conversion. when operat ing in sequence mode, the reference used for each channel is the value written to the ref bit during the last write to the control register. 3, 2 seq1/seq2 the sequence 1 and sequence 2 bits ar e used to control the operation of the sequencer (see table 14 ). 1 weak/ three-state this bit selects the state of the dout line at the end of the current serial transfer. if the bit is set to 1, the dout line is weakly driven to channel address bit add2 of the following conversion. if this bit is set to 0, dout returns to three-state at the end of the serial transfer (see the serial interface section). the eight analog input channels can be configured as seven pseudo differential analog inputs, four pseudo differential inputs, four true differential input pairs, or eight single-ended analog inputs. table 12. analog input configuration selection 7 pseudo differential i/ps 4 fully differential i/ ps 4 pseudo differential i/ps 8 single-ended i/ps channel address bits (mode 1 = 1, mode 0 = 1) (mode 1 = 1, mode 0 = 0) (mode 1 = 0, mode 0 =1) (mode 1 = 0, mode 0 = 0) add2 add1 add0 v in + v in ? v in + v in ? v in + v in ? v in + v in ? 0 0 0 v in 0 v in 7 v in 0 v in 1 v in 0 v in 1 v in 0 agnd 0 0 1 v in 1 v in 7 v in 0 v in 1 v in 0 v in 1 v in 1 agnd 0 1 0 v in 2 v in 7 v in 2 v in 3 v in 2 v in 3 v in 2 agnd 0 1 1 v in 3 v in 7 v in 2 v in 3 v in 2 v in 3 v in 3 agnd 1 0 0 v in 4 v in 7 v in 4 v in 5 v in 4 v in 5 v in 4 agnd 1 0 1 v in 5 v in 7 v in 4 v in 5 v in 4 v in 5 v in 5 agnd 1 1 0 v in 6 v in 7 v in 6 v in 7 v in 6 v in 7 v in 6 agnd 1 1 1 temperature indicator v in 6 v in 7 v in 6 v in 7 v in 7 agnd
ad7329 rev. a | page 27 of 40 table 13. power mode selection pm1 pm0 description 1 1 full shutdown mode. in this mode, all internal circuitry on the ad7329 is powered down. information in the control register is retained when the ad7329 is in full shutdown mode. 1 0 autoshutdown mode. the ad7329 en ters autoshutdown on the 15 th sclk rising edge when the control register is updated. all internal circuitry is powered down in autoshutdown. 0 1 autostandby mode. in this mode, all internal circuitry is powered down, excluding the internal reference. the ad7329 enters autostandby mode on the 15 th sclk rising edge after the control register is updated. 0 0 normal mode. all internal circui try is powered up at all times. table 14. sequencer selection seq1 seq2 description 0 0 the channel sequencer is not used. the analog channel, select ed by programming the add2 to add0 bits in the control register, selects the next channel for conversion. 0 1 uses the sequence of channels that were previously progra mmed in the sequence register for conversion. the ad7329 starts converting on the lowest channel in the sequence. the channels are converted in ascending order. if uninterrupted, the ad7329 keeps converting the sequence. the range for each channel defaults to the range previously written into the corresponding range register. 1 0 this configuration is used in conjunction with the channel address bits in the control register. this allows continuous conversions on a consecutive sequence of channels, from channel 0 through a final channel selected by the channel address bits in the control register. the range for each channel defaults to the range previously written into the corresponding range register. 1 1 the channel sequencer is not used. the analog channel, selected by programming the add2 bit to add0 bit in the control register, selects the next channel for conversion.
ad7329 rev. a | page 28 of 40 sequence register the sequence register on the ad7329 is an 8-bit, write-only register. each of the eight analog input channels has one correspon ding bit in the sequence register. to select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequenc e register. msb lsb 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 write register select 1 register select 2 v in 0 v in 1 v in 2 v in 3 v in 4 v in 5 v in 6 v in 7 0 0 0 0 0 range registers the range registers are used to select one analog input range per analog input channel. range register 1 is used to set the ran ges for channel 0 to channel 3. it is an 8-bit, write-only register with two dedicate d range bits for each of the analog input channels from channel 0 to channel 3. there are four analog input ranges, 10 v, 5 v, 2.5 v, and 0 v to +10 v. a write to range register 1 is selected by setting t he write bit to 1 and the range select bits to 0 and 1, respectively. after the initial write to range register 1 occurs, each time an analog inp ut is selected, the ad7329 automatically configures the analog input to the appropriate range, as indicated by range register 1. the 10 v inpu t range is selected by default on each analog input channel (see table 1 5 ). msb lsb 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 write register select 1 register select 2 v in 0a v in 0b v in 1a v in 1b v in 2a v in 2b v in 3a v in 3b 0 0 0 0 0 range register 2 is used to set the ranges for channel 4 to channel 7. it is an 8-bit, write-only register with two dedicated r ange bits for each of the analog input channels from channel 4 to channel 7. there are four analog input ranges, 10 v, 5 v, 2.5 v, and 0 v to +10 v. after the initial write to range register 2 occurs, each time an analog input is selected, the ad7329 automatically configures the analog input to the appropriate range, as indicated by range register 2. the 10 v input range is selected by default on each analog i nput channel (see table 15 ). msb lsb 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 write register select 1 register select 2 v in 4a v in 4b v in 5a v in 5b v in 6a v in 6b v in 7a v in 7b 0 0 0 0 0 table 15. range selection v in xa v in xb description 0 0 this combination selects the 10 v input range on v in x. 0 1 this combination selects the 5 v input range on v in x. 1 0 this combination selects the 2.5 v input range on v in x. 1 1 this combination selects the 0 v to +10 v input range on v in x.
ad7329 rev. a | page 29 of 40 sequencer operation din: write to range register 1 to select the range for each analog input channel. dout: conversion result from channel 0, 10v range, single-ended mode. cs din: tie din low/write bit = 0 to continue to convert through the sequence of channels. dout: conversion result from first channel in the sequence. cs din: write to sequence register to select the new sequence. dout: conversion result from channel x in the first sequence. cs din: write to range register 2 to select the range for each analog input channel. dout: conversion result from channel 0, single-ended mode, range selected in range register 1. cs din: write to control register to start the sequence, seq1 = 0, seq2 = 1. dout: conversion result from channel 0, single-ended mode, range selected in range register 1. cs din: write to sequence register to select the analog input channels to be included in the sequence. dout: conversion result from channel 0, single-ended mode, range selected in range register 1. cs power on. continuously convert on the selected sequence of channels. din tied low/write bit = 0. select a new sequence. din: write to control register to stop the sequence, seq1 = 0, seq2 = 0. dout: conversion result from channel in sequence. cs stop a sequence. 05402-044 figure 48. programmable sequence flowchart the ad7329 can be configured to automatically cycle through a number of selected channels using the on-chip sequence register with the seq1 bit and the seq2 bit in the control register. figure 48 shows how to program the ad7329 register to operate in sequence mode. these two initial serial transfers are required only if input ranges other than the default ranges are required. after the analog input ranges are configured, a write to the sequence register is necessary to select the channels to be included in the sequence. after the channels for the sequence have been selected, the sequence can be initiated by writing to the control register and setting seq1 to 0 and seq2 to 1. the ad7329 continues to convert the selected sequence without interruption if the sequence register remains unchanged and seq1 = 0 and seq2 = 1 in the control register. after power-up, the four on-chip registers contain default values. each analog input has a default input range of 10 v. if different analog input ranges are required, a write to the range registers is necessary. this is shown in the first two serial transfers of figure 48 .
ad7329 rev. a | page 30 of 40 if a change to one of the range registers is required during a sequence, it is necessary to first stop the sequence by writing to the control register and setting seq1 to 0 and seq2 to 0. next, write to the range register to change the required range. the previously selected sequence should then be initiated again by writing to the control register and setting seq1 to 0 and seq2 to 1. the adc converts the first channel in the sequence. the ad7329 can be configured to convert a sequence of consecutive channels (see figure 49 ). this sequence begins by converting on channel 0 and ends with a final channel as selected by bit add2 to bit add0 in the control register. in this configuration, there is no need for a write to the sequence register. to operate the ad7329 in this mode, set seq1 to 1 and seq2 to 0 in the control register, and then select the final channel in the sequence by programming bit add2 to bit add0 in the control register. after the control register is configured to operate the ad7329 in this mode, the din line can be held low or the write bit can be set to 0. to return to traditional multichannel operation, a write to the control register to set seq1 to 0 and seq2 to 0 is necessary. when seq1 and seq2 are both set to 0 or to 1, the ad7329 is configured to operate in traditional multichannel mode, where a write to channel address bit add2 to bit add0 in the control register selects the next channel for conversion. din: write to range register 1 to select the range for analog input channels. dout: conversion result from channel 0, 10v range, single-ended mode. cs din: write bit = 0 or din line held low to continue through sequence of consecutive channels. dout: conversion result from channel 1, range selected in range register 1. cs din: write to range register 2 to select the range for analog input channels. dout: conversion result from channel 0, range selected in range register 1, single-ended mode. cs din: write bit = 0 or din line held low to continue to convert through the sequence of consecutive channels. dout: conversion result from channel 0, range selected in range register 1. cs din: write to control register to select the final channel in the consecutive sequence, set seq1 = 1 and seq2 = 0. select output coding for sequence. dout: conversion result from channel 0, range selected in range register 1, single-ended mode. cs power on. din tied low/write bit = 0. continuously convert on consecutive sequence of channels. din: write to control register to stop the sequence, seq1 = 0, seq2 = 0. dout: conversion result from channel in sequence. cs stop a sequence. 05402-045 figure 49. flowchart for consecutive sequence of channels
ad7329 rev. a | page 31 of 40 reference the ad7329 can operate with either the internal 2.5 v on-chip reference or an externally applied reference. the internal reference is selected by setting the ref bit in the control register to 1. on power-up, the ref bit is 0, which selects the external reference for the ad7329 conversion. suitable reference sources for the ad7329 include ad780, ad1582, adr431 , ref193 , and adr391 . the internal reference circuitry consists of a 2.5 v band gap reference and a reference buffer. when operating the ad7329 in internal reference mode, the 2.5 v internal reference is available at the ref in /ref out pin, which should be decoupled to agnd using a 680 nf capacitor. it is recommended that the internal reference be buffered before applying it elsewhere in the system. the internal reference is capable of sourcing up to 90 a. on power-up, if the internal reference operation is required for the adc conversion, a write to the control register is necessary to set the ref bit to 1. during the control register write, the conversion result from the first initial conversion is invalid. the reference buffer requires 500 s to power up and charge the 680 nf decoupling capacitor during the power-up time. the ad7329 is specified for a 2.5 v to 3 v reference range. when a 3 v reference is selected, the ranges are 12 v, 6 v, 3 v, and 0 v to +12 v. for these ranges, the v dd and v ss supply must be equal to or greater than the maximum analog input range selected. v drive the ad7329 has a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the ad7329 is operated with a v cc of 5 v, the v drive pin can be powered from a 3 v supply. this allows the ad7329 to accept large bipolar input signals with low voltage digital processing. temperature indicator the ad7329 has an on-chip temperature indicator. the tem- perature indicator can be used to provide local temperature measurements on the ad7329. to access the temperature indicator, the adc should be configured in pseudo differential mode, mode 1 = mode 0 = 1, which sets channel bits add2, add1, and add0 to 1. v in 7 must be tied to agnd or to a small dc voltage within the specified pseudo differential input range for the selected analog input range. when a conversion is initiated in this configuration, the output code represents the temperature (see figure 50 and figure 51 ). when using the temperature indicator on the ad7329, the part should be operated at low throughput rates, such as approximately 30 ksps for the 2.5 v range. the throughput rate is reduced for the temperature indicator mode because the ad7329 requires more acquisition time for this mode. 5450 5050 ?40 80 05402-046 temperature (c) adc output code v cc = v drive = 5v v dd = 12v, v ss = ?12v 2.5v range internal reference 30ksps 5400 5350 5300 5250 5200 5150 5100 ?20 0 20 40 60 figure 50. adc output code vs. temperature for 2.5 v range 4420 4340 ?40 100 temperature (c) adc output code 4410 4400 4390 4380 4370 4360 4350 ?200 20406080 10v range, int ref v cc =v drive =5v v dd /v ss =12v 50ksps 05402-059 figure 51. adc output code vs . temperature for 10 v range
ad7329 rev. a | page 32 of 40 modes of operation the ad7329 has several modes of operation that are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. the mode of operation of the ad7329 is controlled by the power management bits, bit pm1 and bit pm0, in the control register as shown in table 13 . the default mode is normal mode, where all internal circuitry is fully powered up. normal mode (pm1 = pm0 = 0) this mode is intended for the fastest throughput rate performance with the ad7329 being fully powered up at all times. figure 52 shows the general operation of the ad7329 in normal mode. the conversion is initiated on the falling edge of cs , and the track-and-hold section enters hold mode, as described in the section. the data on the din line during the 16 sclk transfer is loaded into one of the on-chip registers if the write bit is set. the register is selected by programming the register select bits (see ). serial interface tabl e 10 11 6 3 channel i.d. bits, sign bit + conversion result data into control/sequence/range1/range2 register sclk cs dout din 05402-047 figure 52. normal mode the ad7329 remains fully powered up at the end of the conversion if both pm1 and pm0 contain 0 in the control register. to complete the conversion and access the conversion result, 16 serial clock cycles are required. at the end of the conversion, cs can idle either high or low until the next conversion. after the data transfer is complete, another conversion can be initiated after the quiet time, t quiet , has elapsed. full shutdown mode (pm1 = pm0 = 1) in this mode, all internal circuitry on the ad7329 is powered down. the part retains information in the registers during full shutdown. the ad7329 remains in full shutdown mode until the power management bits, bit pm1 and bit pm0, in the control register are changed. a write to the control register with pm1 = pm0 = 1 places the part into full shutdown mode. th e ad7329 enters full shutdown mode on the 15 th sclk rising edge when the control register is updated. if a write to the control register occurs while the part is in full shutdown mode with the power management bits, bit pm1 and bit pm0, set to 0 (normal mode), the part begins to power up on the 15 th sclk rising edge when the control register is updated. figure 53 shows how the ad7329 is configured to exit full shutdown mode. to ensure that the ad7329 is fully powered up, t power-up should elapse before the next cs falling edge. cs 11 6 1 sclk sdata din 1 6 invalid data channel identifier bits + conversion result data into control register data into control/shadow register t power-up the p a rt is full y powered up once t power-up has elapsed control register is loaded on the first 15 clocks. pm1 = pm0 = 0 to keep the part in normal mode, load pm1 = pm0 = 0 in control register part is in full shutdown the part begins to power up on the 15th sclk rising edge as pm1 = pm0 = 0 05402-048 figure 53. exiting full shutdown mode
ad7329 rev. a | page 33 of 40 autoshutdown mode (pm1 = 1, pm0 = 0) when the autoshutdown mode is selected, the ad7329 automatically enters shutdown on the 15 th sclk rising edge. in autoshutdown mode, all internal circuitry is powered down. the ad7329 retains information in the registers during autoshutdown. the track-and-hold section is in hold mode during autoshutdown. on the rising cs edge, the track-and- hold section, which was in hold during shutdown, returns to track as the ad7329 begins to power up. the time to power up from autoshutdown is 500 s. when the control register is programmed to transition to autoshutdown mode, it does so on the 15 th sclk rising edge. figure 54 shows the part entering autoshutdown mode. the ad7329 automatically begins to power up on the cs rising edge. the t power-up is required before a valid conversion, initiated by bringing the cs signal low, can take place. after this valid conversion is complete, the ad7329 powers down again on the 15 th sclk rising edge. the cs signal must remain low again to keep the part in autoshutdown mode. autostandby mode (pm1 = 0, pm0 =1) in autostandby mode, portions of the ad7329 are powered down, but the on-chip reference remains powered up. the reference bit in the control register should be 1 to ensure that the on-chip reference is enabled. this mode is similar to autoshutdown but allows the ad7329 to power up much faster, which allows faster throughput rates. as is the case with autoshutdown mode, the ad7329 enters standby on the 15 th sclk rising edge when the control register is updated (see figure 54 ). the part retains information in the registers during standby. the ad7329 remains in standby until it receives a cs rising edge. the adc begins to power up on the cs rising edge. on the cs rising edge, the track-and-hold, which was in hold mode while the part was in standby, returns to track. the power-up time from standby is 750 ns. the user should ensure that 750 ns have elapsed before bringing cs low to attempt a valid conversion. after this valid conversion is complete, the ad7329 again returns to standby on the 15 th sclk rising edge. the cs signal must remain low to keep the part in standby mode. figure 54 shows the part entering autoshutdown mode. the sequence of events is the same when entering autostandby mode. in figure 54 , the power management bits are configured for autoshutdown. for autostandby mode, the power management bits, pm1 and pm0, should be set to 0 and 1, respectively. cs 11 6 15 1 1615 sclk sdata din valid data valid data data into control register data into control register t power-up control register is loaded on the first 15 clocks pm1 = 1, pm0 = 0 part enters shutdown mode on the 15 th rising sclk edge if pm1 = 1, pm0 = 0 p a rt begins to power up on cs rising edge the p a rt is full y powered up once t power-up has elapsed 0 5402-049 figure 54. entering autoshutdown/autostandby mode
ad7329 rev. a | page 34 of 40 power vs. throughput rate the power consumption of the ad7329 varies with throughput rate. the static power consumed by the ad7329 is very low, and significant power savings can be achieved as the throughput rate is reduced. figure 55 and figure 56 show the power vs. throughput rate for the ad7329 at a v cc of 3 v and 5 v, respectively. both plots clearly show that the average power consumed by the ad7329 is greatly reduced as the sample frequency is reduced. this is true whether a fixed sclk value is used or if the sclk value is scaled with the sampling frequency. figure 55 and figure 56 show the power consumption when operating the device in normal mode for a fixed 20 mhz sclk and a variable sclk that scales with the sampling frequency. 12 0 0 1100 05402-050 throughput rate (ksps) average power (mw) 10 8 6 4 2 100 200 300 400 500 600 700 800 900 1000 variable sclk 20mhz sclk v cc = 3v v dd = 12v, v ss = ?12v t a = 25c internal reference figure 55. power vs. throughput rate with 3 v v cc 20 0 0 1000 05402-051 throughput rate (khz) average power (mw) 18 16 14 12 10 8 6 4 2 100 200 300 400 500 600 700 800 900 20mhz sclk variable sclk v cc = 5v v dd = 12v, v ss = ?12v t a = 25c internal reference figure 56. power vs. throughput rate with 5 v v cc
ad7329 rev. a | page 35 of 40 serial interface figure 57 shows the timing diagram for the serial interface of the ad7329. the serial clock applied to the sclk pin provides the conversion clock and controls the transfer of information to and from the ad7329 during a conversion. the cs signal initiates the data transfer and the conversion process. the falling edge of cs puts the track-and-hold section into hold mode and takes the bus out of three-state. the analog input signal is then sampled. once the conversion is initiated, 16 sclk cycles are required for the conversion to complete. the track-and-hold section goes back into track mode on the 14 th sclk rising edge. on the 16 th sclk falling edge, the dout line returns to three-state. if the rising edge of cs occurs before 16 sclk cycles have elapsed, the conversion is terminated and the dout line returns to three-state. depending on where the cs signal is brought high, the addressed register may update. data is clocked into the ad7329 on the sclk falling edge. the three msbs on the din line are decoded to select which register is addressed. the control register is a 12-bit register. if the control register is addressed by the three msbs, the data on the din line is loaded into the control on the 15 th sclk rising edge. if the sequence register or either of the range registers is addressed, the data on the din line is loaded into the addressed register on the 11 th sclk falling edge. conversion data is clocked out of the ad7329 on each sclk falling edge. data on the dout line consists of three channel identifier bits, a sign bit, and a 12-bit conversion result. the channel identifier bits are used to indicate which channel corresponds to the conversion result. if the weak/ three-state bit is set in the control register, rather than returning to true three-state upon the 16 th sclk falling edge, the dout line is pulled weakly to the logic level corresponding to add3 of the next serial transfer. this is done to ensure that the msb of the next serial transfer is set up in time for the first sclk falling edge after the cs falling edge. if the weak/ three-state bit is set to 0 and the dout line returns to true three-state between conversions, then depending on the particular processor interfacing to the ad7329, the add3 bit may be valid in time for the processor to clock it in successfully. if the weak/ three-state bit is set to 1, then although the dout line has been driven to add3 since the previous conversion, it is nevertheless so weakly driven that another device could take control of the bus. this will not lead to a bus contention issue because, for example, a 10 k pull-up or pull-down resister is sufficient to overdrive the logic level of add3. when the weak/ three-state bit is set to 1, the add3 is typically valid 9 ns after the cs falling edge, compared with 14 ns when the dout line returns to three-state at the end of the conversion. add1 1 2 3 4 5 13 14 15 16 write reg sel1 reg sel2 lsb 0 msb add0 sign db11 db10 db2 db1 db0 t 2 t 6 t 4 t 9 t 10 t 3 t 7 t 5 t 8 t 1 t quiet t convert sclk cs dout three- state three-state din add2 3 identification bits 05402-052 figure 57. serial interface timing diagram (control register write)
ad7329 rev. a | page 36 of 40 microprocessor interfacing the serial interface on the ad7329 allows the part to be directly connected to a range of different microprocessors. this section explains how to interface the ad7329 with some of the most common microcontroller and dsp serial interface protocols. ad7329 to adsp-21xx the adsp-21xx family of dsps interfaces directly to the ad7329 without requiring glue logic. the v drive pin of the ad7329 takes the same supply voltage as that of the adsp-21xx. this allows the adc to operate at a higher supply voltage than its serial interface. the sport0 on the adsp-21xx should be configured as shown in table 16 . table 16. sport0 control register setup setting description tfsw = rfsw = 1 alternative framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data-word isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word irfs = 0 internal receive frame sync itfs = 1 internal transmit frame sync the connection diagram is shown in figure 58 . the adsp-21xx has tfs0 and rfs0 tied together. tfs0 is set as an output, and rfs0 is set as an input. the dsp operates in alternative framing mode, and the sport0 control register is set up as described in table 16 . the frame synchronization signal generated on tfs is tied to cs and, as with all signal processing applications, requires equidistant sampling. however, as in this example, the timer interrupt is used to control the sampling rate of the adc, and under certain conditions equidistant sampling cannot be achieved. ad7329 1 adsp-21xx 1 sclk sclk0 cs tfs0 rfs0 dout din dt0 dr0 v dd v drive 1 additional pins omitted for clarity. 05402-053 figure 58. interfacing the ad7329 to the adsp-21xx the timer registers are loaded with a value that provides an interrupt at the required sampling interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and, hence, the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (ax0 = tx0), the state of the serial clock is checked. the dsp waits until the sclk has gone high, low, and high again before starting the transmission. if the timer and sclk are chosen so that the instruction to transmit occurs on or near the rising edge of sclk, data can be transmitted immediately or at the next clock edge. for example, if the adsp-21xx has a master clock frequency of 16 mhz and the sclkdiv register is loaded with the value 3, an sclk of 2 mhz is obtained, and eight master clock periods elapse for every one sclk period. if the timer registers are loaded with the value 803, 100.5 sclks occur between interrupts and, subsequently, between transmit instructions. this situation leads to nonequidistant sampling because the transmit instruction occurs on an sclk edge. if the number of sclks between interrupts is an integer of n, equidistant sampling is implemented by the dsp. ad7329 to adsp-bf53x the adsp-bf53x family of dsps interfaces directly to the ad7329 without requiring glue logic, as shown in figure 59 . the sport0 receive configuration 1 register should be set up as outlined in table 17 . ad7329 1 adsp-bf53x 1 v dd v drive sclk rsclk0 din dt0 dout dr0 cs rfs0 1 additional pins omitted for clarity. 05402-054 figure 59. interfacing the ad7329 to the adsp-bf53x table 17. sport0 receive configuration 1 register setting description rckfe = 1 sample data with falling edge of rsclk lrfs = 1 active low frame signal rfsr = 1 frame every word irfs = 1 internal rfs used rlsbit = 0 receive msb first rdtype = 00 zero fill irclk = 1 internal receive clock rspen = 1 receive enable slen = 1111 16-bit data-word tfsr = rfsr = 1 transmit and receive frame sync
ad7329 rev. a | page 37 of 40 applications information layout and grounding the printed circuit board that houses the ad7329 should be designed so that the analog and digital sections are confined to certain areas of the board. this design facilitates the use of ground planes that can be easily separated. to provide optimum shielding for ground planes, a minimum etch technique is generally best. all agnd pins on the ad7329 should be connected to the agnd plane. digital and analog ground pins should be joined in only one place. if the ad7329 is in a system where multiple devices require an agnd and dgnd connection, the connection should still be made at only one point. a star point should be established as close as possible to the ground pins on the ad7329. good connections should be made to the power and ground planes. this can be done with a single via or multiple vias for each supply and ground pin. avoid running digital lines under the ad7329 device because this couples noise onto the die. however, the analog ground plane should be allowed to run under the ad7329 to avoid noise coupling. the power supply lines to the ad7329 device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. to avoid radiating noise to other sections of the board, com- ponents, such as clocks, with fast switching signals should be shielded with digital ground and never run near the analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feedthrough within the board, traces should be run at right angles to each other. a microstrip technique is the best method, but its use may not be possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to agnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have a low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic and surface-mount types of capacitors. these low esr, low esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. power supply configuration if the supply voltage for the analog input circuitry is different than that of the ad7329 v dd and v ss supplies or if the analog input may be applied to the ad7329 before v dd and v ss are established, it is recommended that schottky diodes be placed in series with the ad7329 v dd and v ss supply signals. figure 60 shows the schottky diode configuration. bat43 schottky diodes are used. 05402-060 v in 0 v in 7 cs sclk dout din v dd v cc v ss ad7329 1 v? v +3v/5 v 1 additional pins omitted for clarity. figure 60. schottky diode connection in an application where nonsymmetrical v dd and v ss supplies are used, adhere to the guidelines provided in table 18 , which outlines the v ss supply range that can be used for various v dd voltages when nonsymmetrical supplies are required. when operating the ad7329 with low v dd and v ss voltages, it is recommended that these supplies be symmetrical. table 18. nonsymmetrical v dd and v ss requirements v dd typical v ss range 5 v ?5 v to ?5.5 v 6 v ?5 v to ?8.5 v 7 v ?5 v to ?11.5 v 8 v ?5 v to ?15 v 9 v ?5 v to ?16.5 v 10 v to 16.5 v ?5 v to ?16.5 v for the 0 v to 4 vref range, v ss can be tied to agnd as per the minimum supply recommendations outlined in table 6 .
ad7329 rev. a | page 38 of 40 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 61. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range package description package option ad7329bruz 1 C40c to +85c 24-lead tssop ru-24 AD7329BRUZ-REEL 1 C40c to +85c 24-lead tssop ru-24 AD7329BRUZ-REEL7 1 C40c to +85c 24-lead tssop ru-24 eval-ad7329cbz 1 , 2 evaluation board eval-control brd2z 1 , 3 controller board 1 z = rohs compliant part. 2 this can be used as a standalone evaluation board or in conjunction with the eval-control board for evaluation/demonstration p urposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices, inc., evaluation boards ending in the cb designators. to order a complete evaluation kit, the pa rticular adc evaluation board (f or example, eval-ad7329cbz), the eval-control brd2z, and a 12 v transformer must be ordered. see the relevant evaluation board technical note on for more information.
ad7329 rev. a | page 39 of 40 notes
ad7329 rev. a | page 40 of 40 notes ?2006C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05402-0-2/10(a)

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